1. Field of the Invention
The present invention relates to a circuit for detecting synchronization errors, and in particular to a circuit that can be usefully combined with a circuit that detects errors in data received in, for example, a digital wireless communication system.
2. Description of the Related Art
The methods generally used for data error control in digital wireless communication systems include cyclic redundancy check (CRC) codes and forward error correction (FEC).
CRC codes enable errors to be detected. Treating the individual bits of transmit data as the coefficients of a polynomial, the transmitting apparatus divides a block of transmit data by a predetermined generator polynomial, and redundantly appends the remainder to the block as a CRC code. The receiving apparatus divides the received block, including the appended CRC code, by the same generator polynomial, and checks that the result is zero. Output of a non-zero bit by the checking circuit indicates that a data error has occurred in the transmission channel.
FEC employs a type of redundant code that has both an error-detecting and an error-correcting capability. Due to the structure of the codes used, however, long burst errors present difficulties for FEC, while the CRC method can detect long burst errors with a fairly high degree of accuracy. The CRC and FEC methods are therefore most effective when they are used selectively, according to the rate of error occurrence and other channel conditions. Not infrequently, the CRC and FEC methods are used in combination.
When the CRC method is used alone, or when the FEC method is used but an error that exceeds the FEC error-correcting capability is detected, a retransmission request is sent to the transmitting apparatus.
Errors may occur in the transmission channel for various reasons, including noise radiating from surrounding areas. When the channel is a wireless channel, errors may also occur because the transmitting apparatus and receiving apparatus are too widely separated and the received radio signal is too weak. Another possible cause is clock jitter in either the transmitting communication apparatus or the receiving communication apparatus. In this case, the channel is regarded as including part of the communication apparatus itself.
The coding theory on which existing methods of error control such as the CRC and FEC methods are based is predicated on the assumption of perfect synchronization between the transmitting and receiving apparatus. If this assumption is not true, error control performance falls short of theoretical expectations.
In actual communication, this assumption is often false. Imperfect synchronization can lead to errors known as bit drop-outs or drop-ins. A drop-out occurs when a bit in the original data stream is deleted in the transmission channel. A drop-in occurs when an originally nonexistent bit is inserted into the data stream in the transmission channel.
Since the CRC and FEC methods assume perfect synchronization, from their coding-theoretical viewpoint, even a single bit drop-out (or drop-in) can cause errors in all the succeeding bits, including the redundant check codes, because a drop-out shifts all succeeding bits forward by one position and a drop-in shifts all succeeding bits back by one position. This can create a very large burst error that can easily exceed not only the FEC error-correcting capability but also the CRC error-detecting capability, making proper error detection impossible.
When the error detection function is realized by the CRC method alone, for example, a typical generator polynomial is g(D)=D16+D12+D5+1. The redundant code generated by this polynomial has sixteen bits, so the number of different check patterns is 65,536 (=216). If errors occur randomly, the probability of a wrong CRC indication is only 1/65,536. More specifically, this is the probability that a random sequence of erroneous bits will defeat the CRC check by fortuitously generating the correct (zero) CRC result. When an error is caused by a bit drop-out or drop-in, however, the probability of a wrong CRC indication is much higher. As a result, it becomes difficult to maintain good communication quality in the face of synchronization errors with their attendant bit drop-ins and drop-outs.